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19-4215; Rev 2; 4/11
KIT ATION EVALU BLE AVAILA
Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
General Description Features
o Supports Up to 840Mbps Data Rate at Each Port o Nonactivated Ports are in High-Impedance State for Easy Port Expansion o Programmable Preemphasis on LVDS Outputs o Self Common-Mode Biasing on LVDS Inputs o Three Selectable Approaches for Switch Routing: I2C Interface LIN Interface Programmable Pins (MAX9134/MAX9135) o 25kV ESD Protection o +3.3V Supply Voltage o -40C to +105C Operating Temperature Range
MAX9132/MAX9134/MAX9135
The MAX9132/MAX9134/MAX9135 high-speed, multiple-port, low-voltage differential signaling (LVDS) crossbar switches are specially designed for digital video and camera signal transmission. These switches have a wide bandwidth, supporting data rates up to 840Mbps. The MAX9132 has three input ports and two output ports, the MAX9134 has three input ports and four output ports, and the MAX9135 has four input ports and three output ports. The digital video or camera signal can go through the switches from an input port to one or multiple output ports. The MAX9132/MAX9134/MAX9135 switch routing is programmable through either an I 2 C interface or a Local Interconnect Network (LIN) serial interface. In addition, the MAX9134/MAX9135 provide pins to set switch routing. These pins also set the initial conditions for the I2C mode. To generate more input or output ports, these switches can be connected in parallel or in cascade. The MAX9132/MAX9134/MAX9135 operate from a +3.3V supply and are specified over the -40C to +105C temperature range. The MAX9134/MAX9135 are available in a 32-pin (5mm x 5mm) TQFP package, while the MAX9132 is available in a 20-pin (6.5mm x 4.4mm) TSSOP package. The input/output port pins are rated up to 25kV ESD for the ISO Air-Gap Discharge Model, 15kV ESD for the IEC Air-Gap Discharge Model, and 10kV for the ESD Contact Discharge Model. All other pins support up to 3kV ESD for the Human Body Model.
Pin Configurations
TOP VIEW
PD 1 DVDD 2 DIN0+ 3 DIN0- 4 DIN1+ 5 DIN1- 6 DIN2+ 7 DIN2- 8 AVDD 9 FS 10
+
20 SCL/RXD 19 SDA/TXD 18 LVDSVDD 17 DOUT0+
MAX9132
16 DOUT015 DOUT1+ 14 DOUT113 LVDSGND 12 AS1/NSLP 11 AS0
Applications
Digital Video in Automotive Video/Audio Distribution Systems Camera Surveillance Systems High-Speed Digital Media Routing Navigation System Displays
TSSOP-EP*
*EXPOSED PAD. CONNECT EP TO GND.
Pin Configurations continued at end of data sheet.
Ordering Information
PART MAX9132GUP+ MAX9132GUP/V+ MAX9134GHJ+ MAX9135GHJ+ PIN-PACKAGE 20 TSSOP-EP* 20 TSSOP-EP* 32 TQFP-EP* 32 TQFP-EP* INPUTS 3 3 3 4 OUTPUTS 2 2 4 3
2
ROUTE CONTROL I2C, LIN I2C, LIN I C, LIN, Pins I2C, LIN, Pins
Note: Devices are specified over the -40C to +105C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part.
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V All Pins to GND .............................................-0.3V to VDD + 0.3V Short-Circuit Duration (all outputs).............................Continuous Continuous Power Dissipation (TA = +70C) 32-Pin TQFP (derate 27.8mW/C above +70C)........2222mW 20-Pin TSSOP (derate 26.5mW/C above +70C) .....2122mW Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) All Other Pins Including SCL, SDA to GND .................2kV IEC 61000-4-2 (RD = 330, CS = 150pF) Contact Discharge (DIN_, DOUT_) to GND ..............................................10kV Air-Gap Discharge (DIN_, DOUT_) to GND ..............................................15kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (DIN_, DOUT_) to GND ..............................................10kV Air-Gap Discharge (DIN_, DOUT_) to GND ..............................................25kV Lead Temperature (soldering, 10s) ................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
20 TSSOP-EP Junction-to-Ambient Thermal Resistance (JA) ........37.7C/W Junction-to-Case Thermal Resistance (JC) ..................2C/W 32 TQFP-EP Junction-to-Ambient Thermal Resistance (JA) ...........36C/W Junction-to-Case Thermal Resistance (JC) ..................4C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = VLVDSVDD = +3.0V to +3.6V, TA = -40C to +105C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C.) (Note 2)
PARAMETER Supply Voltage Supply Current SYMBOL VDD IAVDD, IDVDD, ILVDSVDD SINGLE-ENDED CMOS INPUTS (PD, FS, RXD) Input High Level Input Low Level Input High Current VIH1 VIL1 IIN1 VIN = 0 to VDD -20 VDD 0.4 IOL = 4mA 2.5 0.8 Measured at the input pins VIL3 = 0V or VIH3 = VDD 1.2 -20 1.45 1.9 +20 0.4 2.0 0.8 +20 V V A Outputs switching at 20MHz MAX9132 MAX9134/MAX9135 CONDITIONS MIN 3.0 60 86 TYP MAX 3.6 80 mA 100 UNITS V
SINGLE-ENDED OUTPUTS (TXD, AS1/NSLP) Output High Level Output Low Level 3-LEVEL INPUTS (S5-S0, AS0, AS1) Input High Level Input Low Level Input Open Level Input Current VIH3 VIL3 VIO3 IL3, IH3 V V V A VOH VOL V V
2
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VLVDSVDD = +3.0V to +3.6V, TA = -40C to +105C unless otherwise noted. Typical values are at VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C.) (Note 2)
PARAMETER DIFFERENTIAL INPUTS (DIN_) Differential Input High Threshold Differential Input Low Threshold Common Input Voltage Input Current DIFFERENTIAL OUTPUTS (DOUT_) Differential Output Voltage Change in VOD Between Complementary Output States Output Common-Mode Voltage Change in VCOM Between Complementary Output States Output Short-Circuit Current VOD |VOD| VCOM |VCOM|4 IOS Two output pins connected to GND 50 load, no preemphasis 250 0 1.125 0 -15 0.7 x VDD 0.3 x VDD Open drain with 1k pullup to VDD IOL = 3mA 10 1 0.4 3.65 1 1.29 1 -7 450 35 1.475 35 mV mV V mV mA VIDH VIDL VCOM IIN+, IINVID = VIN+ - VINVID = VIN+ - VINVCOM = (VIN+ - VIN-)/2 -100 1.00 -50 1.29 1.60 +50 100 mV mV V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9132/MAX9134/MAX9135
SERIAL-INTERFACE INPUT, OUTPUT (SCL, SDA) Input High Level Input Low Level High-Level Output Leakage Current Low-Level Output Input Capacitance VIH VIL ILEAKH VOL CI V V A V pF
AC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = VLVDSVDD = +3.0V to +3.6V, TA = -40C to +105C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C.) (Notes 3, 4)
PARAMETER DIFFERENTIAL SIGNALS (DOUT_) Output-to-Output Skew Rise Time tSK tR RL = 100 differential 20% to 80% of the signal swing; RL = 50 differential (RL = 100 double termination), CL = 5pF 20% to 80% of the signal swing; RL = 50 differential (RL = 100 double termination), CL = 5pF Input duty cycle 50%; 840Mbps clock pattern 45 50 0.3 250 0.4 ps ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Fall Time
tF
0.3
0.4
ns
Duty Cycle
D
55
%
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VLVDSVDD = +3.0V to +3.6V, TA = -40C to +105C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C.) (Notes 3, 4)
PARAMETER SYMBOL CONDITIONS VID = 200mV, VCOM = 1.2V, 840Mbps clock pattern; input transition time (20% to 80%) = 200ps tJ VID = 200mV, VCOM = 1.2V, 840Mbps 223 - 1 PRBS pattern; input transition time (20% to 80%) = 200ps tD tLON |VODPE| Switchover time from one channel to another 50 differential (100 double termination) load, 840Mbps 335 530 85 2 100 680 180 ps ns ns mV MIN TYP 10 MAX 30 UNITS ps
Output Peak-to-Peak Jitter (Preemphasis On)
Propagation Delay LVDS Switchover Time LVDS with Preemphasis Amplitude I2C TIMING CLK Frequency Start Condition Hold Time Low Period of SCL Clock High Period of SCL Clock Repeated START Condition Setup Time Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time
fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:STA tSU:STO tBUF (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) 0.6 1.3 0.6 0.6 0 100 0.6 1.3
400
kHz s s s s
0.9
s ns s s
Note 2: Parameters are 100% production tested at TA = +25C, unless otherwise noted. Note 3: I2C timing parameters are specified for fast-mode I2C. Maximum data rate = 400kbps. Note 4: Parameters are guaranteed by design.
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
Typical Operating Characteristics
(VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C, unless otherwise noted.)
MAX9132/MAX9134/MAX9135
SUPPLY CURRENT vs. SUPPLY VOLTAGE
840Mbps 1010 PATTERN PREEMPHASIS +105C 95 -40C NO PREEMPHASIS -40C
MAX9132/4/5 toc01
SUPPLY CURRENT vs. DATA RATE
1010 PATTERN PREEMPHASIS -40C +25C
MAX9132/4/5 toc02
PEAK-TO-PEAK JITTER vs. SUPPLY VOLTAGE
840Mbps PRBS 125 PEAK-TO-PEAK JITTER (ps) 120 115 NO PREEMPHASIS 110 105 100 95 90 85 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) PREEMPHASIS
MAX9132/4/5 toc03
105
105 100 SUPPLY CURRENT (mA) 95 +105C 90 85 80
130
100 SUPPLY CURRENT (mA)
+25C
90
+25C
85 +105C 3.0 3.2 3.4 3.6
-40C +25C +105C NO PREEMPHASIS 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
80
75
SUPPLY VOLTAGE (V)
PEAK-TO-PEAK JITTER vs. TEMPERATURE
MAX9132/4/5 toc04
PEAK-TO-PEAK JITTER vs. DATA RATE
PRBS PATTERN PEAK-TO-PEAK JITTER (ps) 200 NO PREEMPHASIS
MAX9132/4/5 toc05
840Mbps PRBS PEAK-TO-PEAK JITTER (ps) 200 NO PREEMPHASIS 150
CHANNEL-TO-CHANNEL SKEW (ps)
46 47 48 49 50 51 52
150
100
100
50 PREEMPHASIS 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
50
PREEMPHASIS
0 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
53 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
CHANNEL-TO-CHANNEL SKEW vs. DATA RATE
MAX9132/4/5 toc07
EYE DIAGRAM
MAX9132/4/5 toc08
EYE DIAGRAM
200Mbps PRBS WITH PREEMPHASIS 150mV/div
MAX9132/4/5 toc09
35 CHANNEL-TO-CHANNEL SKEW (ps) 30 25 20
1010 PATTERN VDIFF = 200mV
150mV/div
NO PREEMPHASIS
200Mbps PRBS NO PREEMPHASIS
OV 15 10 5 0 100 200 300 400 500 600 700 800 1ns/div PREEMPHASIS
OV
1ns/div
DATA RATE (Mbps)
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MAX9132/4/5 toc06
250
250
45
CHANNEL-TO-CHANNEL SKEW vs. TEMPERATURE
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = VLVDSVDD = +3.3V, TA = +25C, unless otherwise noted.)
EYE DIAGRAM
MAX9132/4/5 toc10
EYE DIAGRAM
150mV/div 840Mbps PRBS WITH PREEMPHASIS
MAX9132/4/5 toc11
150mV/div
840Mbps PRBS NO PREEMPHASIS
OV
OV
200ps/div
200ps/div
Pin Description
PIN MAX9132 TSSOP 1 2 3 4 5 6 -- 7 8 -- -- 9 10 -- -- -- -- 11 MAX9134 TQFP 31 32 1 2 3 4 5 6 7 -- -- 8 -- 9 10 11 12 13 MAX9135 TQFP 30 31 1 2 3 4 -- 5 6 7 8 9 -- 10 11 12 13 14 NAME FUNCTION Power-Down Input. PD = low for power-down. PD = high for power-up without preemphasis. Leave PD open for power-up with preemphasis on all outputs. Digital Power Supply. Bypass DVDD to DGND with 0.1F and 0.01F capacitors as close as possible to the device. Port 0 Positive Input Port 0 Negative Input Port 1 Positive Input Port 1 Negative Input Analog Ground Port 2 Positive Input Port 2 Negative Input Port 3 Positive Input Port 3 Negative Input Analog Power Supply. Bypass AVDD to AGND with 0.1F and 0.01F capacitors as close as possible to the device. I2C and LIN Interface Selection Input. FS = low for LIN, FS = high for I2C. Routing Selection 0 Input. See Tables 6a and 6b. Routing Selection 1 Input. See Tables 6a and 6b. Routing Selection 2 Input. See Tables 6a and 6b. Routing Selection 3 Input. See Tables 6a and 6b. 3-Level I2C Address Selection 0 Input (Table 3) or LIN Identifier Selection 0 Input (Table 4)
PD DVDD DIN0+ DIN0DIN1+ DIN1AGND DIN2+ DIN2DIN3+ DIN3AVDD FS S0 S1 S2 S3 AS0
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
Pin Description (continued)
PIN MAX9132 TSSOP 12 13 -- -- -- -- 14 15 16 17 18 19 20 -- -- -- -- MAX9134 TQFP 14 16, 25 17 18 19 20 21 22 23 24 15, 26 27 28 29 30 -- -- MAX9135 TQFP 15 19, 24 -- -- 17 18 20 21 22 23 16, 25 26 27 28 29 32 -- NAME FUNCTION 3-Level I2C Address Selection 1 Input (in I2C Mode, Table 3). In LIN bus mode, it becomes an NSLP output, the sleep mode activation pin (active low) to the LIN bus driver. LVDS Ground Port 3 Negative Output Port 3 Positive Output Port 2 Negative Output Port 2 Positive Output Port 1 Negative Output Port 1 Positive Output Port 0 Negative Output Port 0 Positive Output LVDS Supply Input. Bypass LVDSVDD to LVDSGND with 0.1F and 0.01F capacitors as close as possible to the device. I2C Data Link Input/LIN Tx Output. SDA/TXD becomes SDA when in I2C mode and TXD when in LIN mode. I2C Clock/LIN Rx Input. SCL/RXD becomes SCL when in I2C mode and RXD when in LIN mode. Routing Selection 5 Input. See Tables 6a and 6b. Routing Selection 4 Input. See Tables 6a and 6b. Digital Ground Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal performance.
MAX9132/MAX9134/MAX9135
AS1/NSLP LVDSGND DOUT3DOUT3+ DOUT2DOUT2+ DOUT1DOUT1+ DOUT0DOUT0+ LVDSVDD SDA/TXD SCL/RXD S5 S4 DGND EP
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Functional Diagrams
DIN0+ DIN0DIN1+ DIN1DIN2+ DIN2FS
DIN0+ DIN0DIN1+ DIN1DIN2+ DIN2S0 S1 S2 S3 S4 S5
ROUTING CONTROL REGISTERS DVDD DGND AVDD AGND LVDSVDD LVDSGND I2C/LIN INTERFACE
PD
ROUTING CONTROL REGISTERS DVDD DGND
PD
SCL/RXD SDA/TXD
AVDD AGND LVDSVDD LVDSGND
I2C/LIN INTERFACE
SCL/RXD SDA/TXD
MAX9132
DOUT1+ DOUT0+ DOUT3+ DOUT2+ DOUT0DOUT3DOUT1DOUT2-
MAX9134 AS0 AS1/ NSLP
DOUT0+ DOUT1+ DOUT0DOUT1-
AS0
AS1/ NSLP
DIN0+ DIN0-
DIN1+ DIN1-
DIN2+ DIN2-
DIN3+ DIN3S0 S1 S2 S3 S4 S5
ROUTING CONTROL REGISTERS DVDD DGND AVDD AGND LVDSVDD LVDSGND I2C/LIN INTERFACE
PD
SCL/RXD SDA/TXD
MAX9135
DOUT0+ DOUT2+ DOUT1+ DOUT0DOUT1DOUT2-
AS0
AS1/ NSLP
8
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 1. Register Address Map
REGISTER ADDRESS (HEX) 0x00 0x01 0x02 0xFF READ/ WRITE R R/W R/W W LIN INTERFACE DESCRIPTION LIN Status Register Switch Control Register 1 Switch Control Register 2 (MAX9134/MAX9135 only) Reserved Reserved Switch Control Register 1 Switch Control Register 2 (MAX9134/MAX9135 only) Route Activation Register I2C DESCRIPTION
SDA tSU:DAT tLOW tHIGH tHD:STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tBUF tHD:STA tSU:STO
tSU:STA
SCL
Figure 1. I2C Serial-Interface Timing Details
Detailed Description
The MAX9132/MAX9134/MAX9135 high-speed, multiple-port, low-voltage differential signaling (LVDS) crossbar switches are specially designed for digital video and camera signal transmission. These switches have a wide bandwidth, supporting data rates up to 840Mbps. This allows the use of MAX9132/MAX9134/ MAX9135 with LVDS serializers/deserializers (SerDes) to create a complete video or camera network. The MAX9132 has three input ports and two output ports, the MAX9134 has three input ports and four output ports, and the MAX9135 has four input ports and three output ports. The video or camera signal can go through the switch from an input port to one or multiple output ports. The MAX9132/MAX9134/MAX9135 switch routing is programmable through either an I 2C interface or a Local Interconnect Network (LIN) serial interface. AS0 and AS1 set the slave addresses for either of these modes, allowing several devices on a bus simultaneously. In addition, the MAX9134/MAX9135 provide 3-level pins S[5:0] to set switch routing and the initial conditions for I2C mode. To improve the signal integrity, all the LVDS outputs feature selectable preemphasis.
Initial Power-Up
On power-up, all control registers have a value of 0x00. For the MAX9134/MAX9135, leaving S[5:0] unconnected, allows control through the LIN interface with all outputs deactivated. Otherwise, the switch runs in pin-control mode with S[5:0] controlling the switch routing. The I2C is also active while the device is in pincontrol mode. Successful routing through I2C overrides the pin settings. For more details, see the I2C Interface section. For the MAX9132, the FS input determines which interface is active.
Register Description
There are four 1-byte control registers in the MAX9132/MAX9134/MAX9135. These registers control the routing of the switch. Table 1 describes the register map for both I 2 C and LIN. When the MAX9132/ MAX9134/MAX9135 operate in LIN mode, register 0x00 acts as an error flag register. Its function is described in detail in Table 5. In either I2C or LIN mode, the control registers (0x01, 0x02) program the MAX9132/ MAX9134/MAX9135 switch routing control. In addition, these registers can individually activate and deactivate preemphasis for each output port. Table 2a describes the routing for the MAX9132/MAX9134 and Table 2b for the MAX9135. For I2C programming, register 0xFF controls the activation of routing.
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 2a. I2C/LIN Switch Routing Control Registers for the MAX9132/MAX9134
REGISTER ADDRESS REGISTER BIT(S) D7 DESCRIPTION DOUT1 Preemphasis VALUE 0 1 000 D[6:4] 0x01 D3 DOUT0 Preemphasis DOUT1 Routing Connection 001 010 011 0 1 000 D[2:0] DOUT0 Routing Connection 001 010 011 D7 DOUT3 Preemphasis 0 1 000 D[6:4] 0x02 (MAX9134 only) D3 DOUT2 Preemphasis DOUT3 Routing Connection 001 010 011 0 1 000 D[2:0] DOUT2 Routing Connection 001 010 011 FUNCTION DOUT1 preemphasis off DOUT1 preemphasis on DOUT1 in high impedance DOUT1 connected to DIN1 DOUT1 connected to DIN0 DOUT1 connected to DIN2 DOUT0 preemphasis off DOUT0 preemphasis on DOUT0 in high impedance DOUT0 connected to DIN1 DOUT0 connected to DIN0 DOUT0 connected to DIN2 DOUT3 preemphasis off DOUT3 preemphasis on DOUT3 in high impedance DOUT3 connected to DIN1 DOUT3 connected to DIN0 DOUT3 connected to DIN2 DOUT2 preemphasis off DOUT2 preemphasis on DOUT2 in high impedance DOUT2 connected to DIN1 DOUT2 connected to DIN0 DOUT2 connected to DIN2
SINGLE WRITE BIT 7.................................. BIT 0 S 7-BIT SLAVE ID 0 ACK BIT AS ADDRESS/COMMAND BYTE BIT 7.....................................BIT 0 ADDR ACK BIT AS BIT 7..........................BIT 0 8-BIT DATA ACK BIT AS P
SINGLE READ BIT 7..........................BIT 0 S 0 ACK BIT AS ADDRESS/COMMAND BYTE BIT 7...............................BIT 0 ACK BIT ADDR AS S BIT 7.........................BIT 0 ACK BIT 7-BIT SLAVE ID 1 AS BIT 7...................BIT 0 ACK BIT 8-BIT DATA /AM P
7-BIT SLAVE ID
ADDR: 8-BIT REGISTER ADDRESS S: 2-WIRE BUS START CONDITION BY MASTER P: 2-WIRE BUS STOP CONDITION BY MASTER AS: ACKNOWLEDGE BY SLAVE AM: ACKNOWLEDGE BY MASTER /AM: NO ACKNOWLEDGE BY MASTER
Figure 2. Single-Byte Write and Single-Byte Read
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 2b. I2C Switch Routing Control Registers for the MAX9135
REGISTER ADDRESS REGISTER BIT(S) D7 DESCRIPTION DOUT1 Preemphasis VALUE 0 1 000 001 D[6:4] DOUT1 Routing Connection 010 011 0x01 D3 DOUT0 Preemphasis 100 0 1 000 001 D[2:0] DOUT0 Routing Connection 010 011 100 D[7:4] D3 0x02 D[2:0] DOUT2 Routing Connection Reserved DOUT2 Preemphasis 0000 0 1 000 001 010 011 100 FUNCTION DOUT1 preemphasis off DOUT1 preemphasis on DOUT1 not connected DOUT1 connected to DIN1 DOUT1 connected to DIN0 DOUT1 connected to DIN2 DOUT1 connected to DIN3 DOUT0 preemphasis off DOUT0 preemphasis on DOUT0 not connected DOUT0 connected to DIN1 DOUT0 connected to DIN0 DOUT0 connected to DIN2 DOUT0 connected to DIN3 Set these bits to 0000 DOUT2 preemphasis off DOUT2 preemphasis on DOUT2 not connected DOUT2 connected to DIN1 DOUT2 connected to DIN0 DOUT2 connected to DIN2 DOUT2 connected to DIN3
I2C Interface
The MAX9132/MAX9134/MAX9135 operate as slaves that send and receive data through I2C (see Figure 1). The interface uses a serial-data line (SDA) and a serialclock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the slave and generates the SCL clock that synchronizes the data transfer. The SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. The SCL line operates only as an input. A pullup resistor is required on SCL if there are multiple masters on the I2C interface, or if the master in a single-master system has an opendrain SCL output. Each transmission consists of a START condition sent by a master, followed by the 7-bit slave address plus R/W bit, a register address byte, a data byte, and finally a STOP condition. Table 3 shows the slave address selection by the AS0 and AS1 pins.
Data Format for Writing to the Slave A write to the MAX9132/MAX9134/MAX9135 comprises the transmission of the slave address with the R/W bit set to 0, followed by at least 1 byte of information. The first byte of information is the command byte. The command byte determines which registers of the MAX9132/MAX9134/MAX9135 are to be written by the next byte, if received. If a STOP condition is detected after the command byte is received, the MAX9132/ MAX9134/MAX9135 take no further action beyond storing the command byte. Any bytes that are received after the command byte are data bytes. The first data byte goes into the internal register of the crossbar switch selected by the command byte (Figure 2). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX9132/MAX9134/MAX9135 internal registers because the command byte address generally autoincrements (Table 1).
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 3. I2C Slave Addresses
PIN AS0 Low Low Low Open Open Open High High High AS1 Low Open High Low Open High Low Open High A[7:5] 101 101 101 101 101 101 101 101 101 A4 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 ADDRESS A3 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W ADDRESS (HEX) 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0XAC 0xAE 0xB0
FRAME SLOT FRAME RESPONSE SPACE INTERFRAME SPACE
HEADER
RESPONSE
BREAK
SYNC
PROTECTED INDENTIFIER
DATA 1
DATA 2
DATA N*
CHECKSUM *N = 2 FOR WRITE AND 4 FOR READ
TRANSMITTED FROM MASTER
TRANSMITTED FROM A MASTER OR SLAVE
Figure 3. LIN Bus Signal Format
WRITE FORMAT 0x01 DATA 1 0x02 DATA 2 0x00 DATA 1 READ FORMAT 0x01 DATA 2 0x02 DATA 3 0xFF DATA 4
Figure 4. LIN Write and Read Data Frame
Data Format for Reading from the Slave The MAX9132/MAX9134/MAX9135 are read using the devices' internally stored command bytes as an address pointer, the same way the stored command byte is used as an address pointer for a write. The pointer does not autoincrement after each data byte is read. Initiate a read by writing the command byte to the proper slave address (Figure 2), then send the device's slave address with the R/W bit set to 1. The slave now responds with the contents of the requested register (Figure 2).
LIN Interface
The LIN interface is a low-speed, low-cost interface used in slow control signal traffic in automotive applications. This device is the slave node in the LIN bus cluster and is designed based on the LIN Rev. 1.3 specification. The LIN master sends data to the MAX9132/MAX9134/ MAX9135 LSB first, up to a maximum data rate of 20kbps. The LIN slave node waits for the synchronization pulse, then synchronizes itself to the pulse. The node must then read the identifier and send/receive data bytes to the master, setting the error flag register when necessary. The LIN interface uses the same routing function of the switch control registers (0x01, 0x02) as the I2C inter-
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 4. LIN Identifiers for Write and Read Operations
AS0 Low Open High WRITE ID ID[5:0] 0x08 0x0A 0x1C PID FIELD 0x08 0xCA 0x9C ID[5:0] 0x27 0x29 0x2B READ ID PID FIELD 0xE7 0xE9 0x2B
Table 5. Register 0x00 Error Flag Mapping for LIN
REGISTER BIT(S) D[7:5] D4 D3 D2 D1 D0 DESCRIPTION Reserved Sync Transmit Checksum Parity Frame Reserved Sync pulse widths outside the given tolerances detected Value read on RXD different from value transmitted on TXD during a read Checksum sent during a write does not match the expected checksum ID parity bit does not match expected parity Message frame did not complete within the maximum allowed time FUNCTION
face. The routing action takes place after correct checksum verification. The LIN status register (0x00) holds the error flags for the LIN transceiver. For a write, the master writes 2 bytes of data to the registers (0x01, 0x02). For a read, the slave outputs the contents of registers 0x00, 0x01, and 0x02, along with the stuffing byte at a constant value (0xFF). In either mode, the checksum follows at the end of the data bytes. Figure 3 shows the write and read signal frame format. Figure 4 shows the LIN write and read data frame.
VDD
VBAT
5k 5k MAX9132 MAX9134 MAX9135 TXD RXD NSLP 5k INH TXD RXD NSLP LIN LIN BUS NWAKE MAX13020
LIN-Protected Identifier The LIN bus uses the 8-bit protected identifier (PID) to address the slave nodes. Two parity bits (MSBs) along with 6 ID bits (LSBs) make up the PID field. Table 4 defines the sets of the identifiers for the write/read operations of the LIN slave node. AS0 selects the identifiers. AS1/NSLP becomes the NSLP output for activating the LIN driver chip (MAX13020). LIN Error Handling Register 0x00 contains the error flags found in the LIN signal by the slave note (Table 5). A successful LIN read resets register 0x00.
Figure 5. Connecting the MAX9132/MAX9134/MAX9135 to the MAX13020
registers 0x01 and 0x02 take over the routing and the pin (S[5:0]) setting is ignored. After the I 2C routing takes place, the pin setting can be changed without affecting the routing. The new pin setting takes effect if the PD pin or the chip supply is toggled. Usually, once I2C controls the routing, there is no value in using the pin routing.
Pin Control by S[5:0] (MAX9134/MAX9135)
For the MAX9134/MAX9135, the routing can be controlled by the hardware pins (S[5:0]). If the I2C register 0xFF is not written by 0xFF, then chip routing is determined by S[5:0]. Also, these pins set the initial powerup routing condition of the chip. Table 6a gives the details of the routing control for the MAX9134. Table 6b gives the details of the routing control for the MAX9135. Once the I2C register 0xFF is written by 0xFF, the I2C
Applications Information
3-Level Inputs
The MAX9132/MAX9134/MAX9135 use several 3-level inputs to control the device. Use three-state logic to realize the 3-level logic using digital control. Alternatively, if a high-impedance output is unavailable, apply a voltage of VDD/2 to realize the midlevel highimpedance state.
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 6a. Switch Routing Control Pin Setting for the MAX9134
PORT S5 S4 S3 S2 S1 X 0 X X X 0 Open 1 DOUT0, DOUT1 1 X X X Open 0 X X X 0 Open 1 0 Open 1 1 X X X 0 X X 0 0 Open 1 DOUT2, DOUT3 X 1 Open 0 0 Open 1 0 Open 1 X 1 1 X X X X X X X X Open 1 X X 1 X X S0 0 Open 1 CONNECTION DOUT0 connected to DIN0 DOUT0 connected to DIN1 DOUT0 connected to DIN2 DOUT1 connected to DIN0 DOUT1 connected to DIN1 DOUT1 connected to DIN2 DOUT0 connected to DIN0 DOUT0 connected to DIN1 DOUT0 connected to DIN2 DOUT1 connected to DIN0 DOUT1 connected to DIN1 DOUT1 connected to DIN2 DOUT0 and DOUT1 in high impedance DOUT2 connected to DIN0 DOUT2 connected to DIN1 DOUT2 connected to DIN2 DOUT3 connected to DIN0 DOUT3 connected to DIN1 DOUT3 connected to DIN2 DOUT2 connected to DIN0 DOUT2 connected to DIN1 DOUT2 connected to DIN2 DOUT3 connected to DIN0 DOUT3 connected to DIN1 DOUT3 connected to DIN2 DOUT2 and DOUT3 in high impedance Both DOUT2 and DOUT3 are not connected DOUT2 is not connected, DOUT3 is on DOUT3 is not connected, DOUT2 is on Both DOUT2 and DOUT3 outputs are on Both DOUT0 and DOUT1 are not connected DOUT0 is not connected, DOUT1 is on DOUT1 is not connected, DOUT0 is on Both DOUT0 and DOUT1 outputs are on DESCRIPTION
X = Don't care.
Interface Selection Using S[5:0] (MAX9134/MAX9135)
S[5:0] determine which interface controls the MAX9134/MAX9135. Leave S[5:0] unconnected or set to a midlevel state to enable the LIN interface. Other settings to S[5:0] set the switch routing according to Tables 6a (MAX9134) and 6b (MAX9135). The I2C interface is active when the MAX9132/MAX9134/MAX9135 are not in LIN interface mode. Writing to an I2C register overrides the S[5:0] settings.
Interface Selection Using FS (MAX9132 Only)
The FS input selects the interface for the MAX9132. Set FS low for LIN interface control and FS high for I2C interface. The MAX9132 powers up with all LVDS outputs unconnected for either mode.
Interfacing the MAX9132/MAX9134/MAX9135 to the LIN Bus
The MAX9132/MAX9134/MAX9135 interface to the LIN bus through the MAX13020 LIN transceivers. This device translates the +12V to +42V LIN bus signal down
14
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Table 6b. Switch Routing Control Pin Setting for the MAX9135
PORT S5 0 0 DOUT0 0 1 1 X 0 0 DOUT1 X 0 1 1 X 0 0 DOUT2 X X 0 1 1 X 0 Open 1 0 Open X X X X X X X 0 Open 1 0 Open X X X X X S4 S3 S2 S1 S0 0 Open 1 0 Open CONNECTION DOUT0 connected to DIN0 DOUT0 connected to DIN1 DOUT0 connected to DIN2 DOUT0 connected to DIN3 DOUT0 in high impedance DOUT1 connected to DIN0 DOUT1 connected to DIN1 DOUT1 connected to DIN2 DOUT1 connected to DIN3 DOUT1 in high impedance DOUT2 connected to DIN0 DOUT2 connected to DIN1 DOUT2 connected to DIN2 DOUT2 connected to DIN3 DOUT2 in high impedance S3 and S2 determine DOUT2 connection S4 and S1 determine DOUT1 connection S5 and S0 determine DOUT0 connection DESCRIPTION
X = Don't care.
to the +3.3V logic level. Figure 5 shows the circuit that interfaces the crossbar switches to the LIN bus.
Waking Up the LIN Bus Driver At power-up, the MAX9132/MAX9134/MAX9135 leave NSLP low, keeping the LIN bus driver in sleep mode. When the LIN driver receives a wake-up signal (Figure 6) from the LIN bus, the driver pulls RXD low. When the MAX9132/MAX9134/MAX9135 detect a falling edge on RXD, the device pulls NSLP high waking up the LIN driver. The MAX9132/MAX9134/MAX9135 then enable the TXD pin. Putting the LIN Bus Driver into Sleep Mode There are two conditions under which the MAX9132/ MAX9134/MAX9135 put the LIN driver to sleep: line activity timeout and receiving a sleep command. The first condition arises if there is inactivity on the LIN bus
for more than 3s. The second condition requires sending the data 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF using the identifier 0x3C to the device. If any of the two conditions happen, the device disables TXD and drives NSLP low. This puts the LIN driver into sleep mode.
Multiple MAX9132/MAX9134/MAX9135 for Port Expansion
The MAX9132/MAX9134/MAX9135 high-impedance outputs allow the attachment of several parts in parallel. Figure 7 shows example connection schemes to realize larger crossbar connections.
LVDS Output Preemphasis
The MAX9132/MAX9134/MAX9135 feature a preemphasis mode where extra current is added to the output and causes the amplitude to increase by 50% at the transition point. Preemphasis helps to get a faster transition, better eye diagram, and improved signal integrity (see the Typical Operating Characteristics). During data transition, the switch injects additional current for a short period, typically 400ps. Leave PD open or apply a midlevel voltage (VDD/2) to enable preemphasis on all LVDS outputs. Set PD high to set preemphasis through the I2C or LIN interfaces. Preemphasis in this mode is initially not on.
> 30s RXD
Power-Down
Set PD low to enable power-down mode. The registers retain their values and the device resumes operation from the same mode upon power-up.
15
Figure 6. LIN Bus Wake-Up Signal
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
DIN1 DIN2 DIN3 DIN1 DIN2 DIN3
MAX9134
MAX9134
DIN1
DIN2
DIN3
DIN1
DIN2
DIN3
DOUT1
DOUT2
DOUT3
DOUT4
DOUT1
DOUT2
DOUT3
DOUT4
MAX9134
MAX9134
DOUT1
DOUT2
DOUT3
DOUT4
DOUT1
DOUT2
DOUT3
DOUT4
3 x 8 SWITCH
6 x 4 SWITCH
Figure 7. Topologies for Port Expansion
Input/Output Termination
Terminate LVDS inputs/outputs through 100 differential termination, or use an equivalent Thevenin termination. Terminate both inputs/outputs and use identical terminations on each for the lowest output-to-output skew.
automated test equipment. Make the PCB traces that make up a differential pair the same length to avoid skew within the differential pair.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic-field-canceling effects. Balanced cables pick up noise as common mode that is rejected by the LVDS receiver. Add a 0.1F capacitor in series with each output for AC-coupling.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass each supply to their respective grounds with highfrequency surface-mount 0.01F ceramic capacitors as close as possible to the device. Use multiple bypass vias for connection to minimize inductance.
Board Layout
Separate the I2C/LIN signals and LVDS signals to prevent crosstalk. When possible, use a four-layer PCB with separate layers for power, ground, LVDS, and digital signals. Layout PCB traces for 100 differential characteristic impedance. The trace dimensions depend on the type of trace used (microstrip or stripline). Route the PCB traces for an LVDS channel (there are two conductors per LVDS channel) in parallel to maintain the differential characteristic impedance. Place the 100 (typ) termination resistor at both ends of the LVDS driver and receiver. Avoid vias. If vias must be used, use only one pair per LVDS channel and place the via for each line at the same point along the length of the PCB traces. This way, any reflections occur at the same time. Do not make vias into test points for
16
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high level to data and clock lines. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for a data rate up to 400kbps (see the I2C Interface section for details). To meet the rise time requirement, choose the pullup resistors so that the rise time tR = 0.85RPULLUP x CBUS < 300ns. If the transition time becomes too slow, the setup and hold times may not be met and waveforms are not recognized.
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
Exposed Pad
The TQFP and TSSOP packages used for the MAX9132/MAX9134/MAX9135 have exposed pads on the bottom. The exposed pad is internally connected to ground. Connect the exposed pad to ground using a landing pad large enough to accommodate the entire exposed pad. Add vias from the exposed pad's land area to a copper polygon on the other side of the PCB to provide lower thermal impedance from the device to the ambient air. discharge components are C S = 100pF and R D = 1.5k (Figure 9). For the Human Body Model, all pins are rated for 2kV Contact Discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 10). For ISO 10605, the LVDS outputs are rated for 10kV Contact and 25kV Air-Gap Discharge.
MAX9132/MAX9134/MAX9135
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
ESD Protection
The MAX9132/MAX9134/MAX9135 ESD tolerance is rated for IEC 61000-4-2, Human Body Model, and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330 (Figure 8). For IEC 61000-4-2, the LVDS outputs are rated for 10kV Contact Discharge and 15kV Air-Gap Discharge. The Human Body Model
Figure 9. Human Body ESD Test Circuit
RD 330 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 330pF
RD 2k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 8. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 10. ISO 10605 Contact Discharge ESD Test Circuit
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17
Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Typical Application Circuit
LVDS INPUTS
0.1F 100 x 3 VDD DIN0+ DVDD AVDD MAX9134 DIN0DIN1+ DIN1DIN2+ DIN2-
CONNECT S[5:0] ACCORDING TO DESIRED INITIAL ROUTING VDD S0 S1 S2 S3 S4 S5
RPU SCL/RXD SDA/TXD
RPU
AGND LVDSVDD
TO I2C MASTER
LVDSGND DOUT0+ 100 x 4 0.1F DOUT0- DOUT1+ DOUT1- DOUT2+ DOUT2- DOUT3+ DOUT3AS0 AS1/NSLP
LVDS OUTPUTS
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches
Pin Configurations (continued)
LVDSGND LVDSGND DOUT0+ DOUT1+ DOUT2+ DOUT3+ DOUT0+ DOUT1+ DOUT2+ DOUT0DOUT1DOUT2DOUT3DOUT0DOUT1DOUT2-
MAX9132/MAX9134/MAX9135
TOP VIEW
TOP VIEW
24
23
22
21
20
19
18
17
24
23
22
21
20
19
18
17
LVDSGND 25 LVDSVDD 26 SDA/TXD 27 SCL/RXD 28 S5 29 S4 30 PD 31 DVDD 32
16 LVDSGND 15 LVDSVDD 14 AS1/NSLP 13 AS0
LVDSVDD 25 SDA/TXD 26 SCL/RXD 27 S5 28 S4 29 PD 30 DVDD 31 DGND 32
16 LVDSVDD 15 AS1/NSLP 14 AS0 13 S3
MAX9134
12 S3 11 S2
MAX9135
12 S2 11 S1
+
10 S1 9 S0
+
10 S0 9 AVDD
1 DIN0+
2 DIN0-
3 DIN1+
4 DIN1-
5 AGND
6 DIN2+
7 DIN2-
8 AVDD
1 DIN0+
2 DIN0-
3 DIN1+
4 DIN1-
5 DIN2+
6 DIN2-
7 DIN3+
8 DIN3-
TQFP-EP*
*EXPOSED PAD. CONNECT EP TO GND.
TQFP-EP*
*EXPOSED PAD. CONNECT EP TO GND.
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 20 TSSOP-EP 32 TQFP-EP PACKAGE CODE U20E+1 H32E+6 OUTLINE NO. 21-0108 21-0079 LAND PATTERN NO. 90-0114 90-0326
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Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches MAX9132/MAX9134/MAX9135
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 7/08 2/11 4/11 Initial release Updated Pin Control by S[5:0] (MAX9134/MAX9135) and Interface Selection Using FS (MAX9132 Only) sections Added automotive part (MAX9132) to Ordering Information DESCRIPTION PAGES CHANGED -- 13, 14 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 20
(c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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